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How To Test Your ORS Radio Board PCB

How To Test Your ORS Radio Board PCB
  • Last Update:2023-03-03
  • Version:001
  • Language:en


  • Requirements
  • Environment Setup
  • Voltage Measurement
  • Radio Test Setup
  • Radio Test
  • Conclusion
This initial test can be operated right after the fabrication of the PCB.


Environment Setup


Prepare to power on the PCB as shown in the photo.

Initial power: 24V, 200mA max to ensure there is no severe short circuits. 

Operation power: 24V, 3A max.


Install the PCB in the shield box, make sure that the board is well attached to the thermal paste.


Voltage Measurement

Bottom Side

1. Connect power cable to the connector PS0 without connecting to the mini PC. Set the power to 24V 200mA and turn on the power supply. If there is no severe short circuit, the current is supposed to be around 105mA when the FPGA is not flashed. And then set the delivery power to 24V 3A.

2. Test the voltage on each Test point.

  • PS0:
    • Power the PCB on with 24V 200mA max for the first time without connecting the mini PC.
    • Operation/Test mode: 24V 3A max.
  • TP1: 12V
  • TP2: 5V
  • TP3: 5V

*TP: test point
*PS0: Power supply


Top side

  • TP4: 1V8
  • TP5: 1V8
  • TP6: 2V5
  • TP7: 1V2
  • TP8: 3V3
  • TP9: 1V3
  • TP10: 3V3

Radio Test Setup

Device setup

1. Disconnect power cable on PS0.
2. Connect the PC and the PCB as the picture shown above. There are 3 cables linking the PC and the PCB : Ethernet cable, Power cable, FFC cable. (Attention: the power cable of PC is connected to the port PWR_PC)
3. Connect the PoE cable. The power input for the entire device is via PoE.
4. Connect MCX cables to the two output channels ANT1 and ANT2. Add at least 30dB external attenuation nodes before connecting to Signal Analyzer. (Attention: please verify the tolerance of your signal analyzer)
5. Connect the signal output after the attenuation nodes to the Signal Analyzer.

Flash firmware of FPGA

1. ssh to the mini PC.
2. In the root directory, clone ors-utils-private :

root@orsLAB:~# git clone https://lab.nexedi.com/nexedi/ors-utils-private
* if the folder already exists, do git pull.

3. Check sdr in system messages. 

root@orsLAB:~# dmesg | grep sdr
[   24.738399] sdr: loading out-of-tree module taints kernel.
[   24.738432] sdr: module verification failed: signature and/or required key missing - tainting kernel

 4. If get messages above, the FPGA on PCB is not flashed.  Go to directory ~/flash-trxsdr/openocd/. Follow the commands below to flash the FPGA.


root@orsLAB: cd flash-trxsdr/openocd
root@orsLAB:~/flash-trxsdr/openocd# ./bootstrap
root@orsLAB:~/flash-trxsdr/openocd# ./configure --enable-ftdi
root@orsLAB:~/flash-trxsdr/openocd# cd ..
root@orsLAB:~/flash-trxsdr# ./openocd/src/openocd -s ./openocd/tcl -f pcie_radio.cfg

* the flashing process takes about 1 minute.

 5. Once the flashing finished, reboot the PC, and the ssh to the PC again.

root@orsLAB:~/flash-trxsdr# poweroff

 6. After reboot, check sdr in system message, the PCI device is supposed to be detected.

root@orsLAB:~# dmesg | grep sdr
[   19.289344] sdr: loading out-of-tree module taints kernel.
[   19.289378] sdr: module verification failed: signature and/or required key missing - tainting kernel
[   19.289655] sdr Probing device
[   19.289667] sdr 0000:01:00.0: enabling device (0000 -> 0002)
[   19.294534] sdr CDCM6208_initialize (VCXO 38.4MHz)
[   21.293209] sdr cdcm6208: timeout while waiting for PLL lock
[   21.333269] sdr PCI device 01:00.0 assigned to minor 0, type=RF_SDR50 (rev 0)
[   21.333273] sdr FPGA Revision: 2021-10-8

* if PCB is not detected, run init.sh in directory /trx_sdr/kernal/, and do command above again to check if the PCB is detected.
root@orsLAB:~# cd trx_sdr/kernel/
root@orsLAB:~/trx_sdr/kernel# ./init.sh

Radio Test

1. In directory ~/trx_sdr/, run sdr_play (Read Warning before run the command)

Warning :

  • Replace [XXXX] with the correct signal generation file name, which depends on the version and band freq of the PCB.
  • Change [tx_freq 2600e6] parameter to the frequency corresponding to the band frequency. (e.g. Board TDD Band42 = tx_freq 3500e6)
  • Change sample rate [rate 30.72e6] to the correct value which is corresponding to the signal generation file name. (e.g. LTE-TM_31-20MHz_SR30720000-TDD-ADJUSTED.bin requires the sample rate 30720000Hz = 30.72e6.)
  • Choose a proper [tx_gain] value to control output power from the radio PCB. Choose [tx_gain] value between [mid] to [high] shown in the table below. For first time test, set the tx_gain to the lowest power [mid].
  • [-channels 2] stands for output signal on both 2 channels. Do Not change. 
Band mid high
38 60 79
39 60 88
42 60 83
43 60 77

root@orsLAB:~/trx_sdr# ./sdr_play ~/ors-utils-private/matlab/signal-generation/waveform/XXXX ~/ors-utils-private/matlab/signal-generation/waveform/XXXX -tx_freq 2600e6 -rate 30.72e6 -tx_gain 60 -channels 2 -loop

2. After these parameter are correctly configured,  run command. In signal analyzer, set the matched signal frequency and bandwidth.

3. Gradually increase the output power in the range from [mid] to [high]. 



Validate initial condition of the PCB, next step